As microelectronic packaging technology advances for higher processor performance, improving adhesion between package underfill materials and connective interconnect materials, such as copper bump material, remains an important issue. Adhesion between the two materials can be challenging due to a tendency to have very poor chemical bonding as well as coefficient of thermal expansion (CTE) mismatch between such materials as copper and epoxy. In fact, delamination between an underfill material and copper surfaces may occur under high mechanical and thermal stress conditions. Such delamination can propagate in an upwards direction and can cause package passivation layers to crack, or the delamination may propagate in a downwards direction and can cause solder resist materials to crack, which may further result in copper trace cracking at a package substrate level. Delamination in either direction can lead to package electrical failure and reliability issues.